Forgive me, fellow Digital Design geeks, for I have sinned. Faced with a lack of 74LS245 tristate buffer ICs (I swear they were in the cabinet last week), I have created a truly ugly hack.
The latest iteration of the 8-bit DrACo/Z80 design uses a PIC16F688 as a custom 8-bit up/down counter, to run the address lines. This should make it quite a bit easier to program than previous designs, while not making the design any more complex. The data bus is now run straight from the logic switches on the CADET II trainer into a single 74LS245 tristate buffer chip. When writing to the data bus manually, the ’245 is enabled and the eight bits from the switches are copied onto the data bus. Otherwise, the ’245 is disabled (tristated), allowing the Cypress memory chip or the Z80 to control the data bus. We’ve been using this design for three or four years now, and it works nicely.
The lack of available ’245s, though, meant that the logic switches would be continually driving the bus, contending with the output from the memory chip if it were enabled for a read. Bus contention is a Bad Thing™ — because it not only causes chaotic computer behavior, but can actually damage components due to two low-impedance sources driving the same net. The ’245 prevents this, since it is set to only enable its outputs when nothing else is driving the data bus. Without it, the system will work incorrectly and could possibly burn itself out.
solution ugly hack workaround was to connect the switches to the data bus via 470-ohm resistors. (I would have used 1ks, but there weren’t as many of those handy.) When the switches are the only thing driving the bus, they should still have low enough impedance to assert the correct values onto the data bus. When the memory is driving the data bus (during a read), its low-impedance output (20mA) should be enough to overcome any resistors pulling in the opposing direction.
It should work for now, but it’s definitely ugly.