…but can it compute?
As it turns out, the native “A * ~B” gate (see “Boolean Logic with 555s“) can be made into a S/R latch, with the addition of a few resistors and a diode. (The 555 actually does contain such a latch inside it, but not all of the latch ports are exposed as pins.) The diode is needed to block a low (inactive) signal from the Set pin from resetting the circuit when it is in the on state. The reset resistor (connected to DIS/CON, not RST) may not be needed; this design was hastily done in time for the 555 contest and I went with the first implementation that worked.
This S/R latch circuit allows a 555 to function as one bit of static RAM. With enough 555s — and no other active components – a primitive (but Turing-complete!) computer can therefore be built, using only 555s! (For this implementation, I’m using diodes, which are technically active, but even these are not essential. Given enough 555s; S/R latches can be built from logic gates alone, which can be built from 555s, as demonstrated in another post. The diodes do help reduce the circuit size quite a bit, though.)
One tricky factor is the lack of tristate output functionality; the 555′s output is always high or low, never tristated. This can be mitigated by using OR gates (a NOR cascade with a final inverter, as shown below) to combine the various possible sources onto a single bus. As long as only one source is active at a time, its data will be carried through correctly — and no electrical contention (shorted outputs) is ever possible, even if more than one source does go active/high at one time. Multiplexing N outputs into a single line via OR logic therefore requires N+1 555s. (This could also probably be done with diodes and a pulldown resistor, but the eventual goal is an all-555 design.)
Since using 555s as logic gates is extremely inefficient in terms of space and wiring complexity, the computer design is necessarily quite simple. A six-bit word size allows for orthogonal instructions: 2-bit opcodes with 4-bit operands. This will allow for four possible operations, and 4-bit operands ranging from 0 to 15. Twenty-six or so 555s are needed for each word of memory, plus extras to combine them onto the output lines, so I have built just four six-bit words for the time being, rather than completing all sixteen possible memory locations. Another six-bit word for the accumulator has been completed, along with a four-bit word for the program counter. The 2-to-4 address decoder for the memory is complete (visible on the breadboard at the side). The rest of the control and processing logic is planned but not built at this point. Here’s the planned block diagram:
Here’s a picture of the memory subsystem:
Here is a video of the memory in action (storing several words of data). The LEDs show the state of the memory; with the addition of a (mostly complete) NOR cascade multiplexer, the memory will be capable of outputting its data onto a single data bus. With the addition of a (completed but buggy) address demultiplexer, the memory subsystem will be ready to take its place in the 555 computer.
Unfortunately, lack of time (I get to do a lot of interesting things at my day job, but they do seem to insist that I show up for work) has prevented me from completing the entire design in time for the contest — but the design is feasible. Hopefully, I’ll be able to have the whole thing up and working sometime this summer. If so, I’ll post the details here.